A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications-Reference-Cited by-同舟云学术

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A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Published:2015-06 Issue: Volume: Page:
ISSN:
Container-title:2015 Symposium on VLSI Circuits (VLSI Circuits)
language:
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Author:

Jung Hae-Kang,Yang Jaemo,Lee Jeonghun,Ko Hyeongjun,Lee Hyuk,Song Taeksang,Shim Jongjoo,Lee Sang-Kwon,Song Keunsoo,Kim Dong-Kyun,Kim Hyungsoo,Kim Yunsaing

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7196579/7231231/07231255.pdf?arnumber=7231255

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Time Controlled Pre-Emphasis Circuit for Broadband Frequency Operation up to 3.6 Gbps;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-08

3. A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-11

4. A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface;IEEE Access;2022

5. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation;IEEE Journal of Solid-State Circuits;2022-01

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