Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed solid-state drives (SSD)
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4573021/4585928/04585977.pdf?arnumber=4585977
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Embedded multiport data buffer for a solid-state drive controller;IEICE Electronics Express;2021-05-10
2. Challenges of Flash Memory for Next Decade;2021 IEEE International Reliability Physics Symposium (IRPS);2021-03
3. A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories;Solid-State Electronics;2016-07
4. (Invited) Storage Class Memory and NAND Flash Memory Hybrid Solid-State Drives (SSD);ECS Transactions;2013-08-31
5. NAND and Controller Co-design for SSDs;Inside Solid State Drives (SSDs);2012-08-31
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