A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-μm cost-effective DRAM technology
Author:
Publisher
Widerkehr and Associates
Link
http://xplorestaging.ieee.org/ielx5/9331/29642/01346553.pdf?arnumber=1346553
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-01
2. Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation;IEICE Transactions on Electronics;2007-04-01
3. Low-Voltage Embedded RAMs in Nanometer Era;IEICE Transactions on Electronics;2007-04-01
4. An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme;IEEE Journal of Solid-State Circuits;2007-01
5. A new type of SRAM using DRAM technology;Electronics and Communications in Japan (Part II: Electronics);2007
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