An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme-Reference-Cited by-同舟云学术

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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

Published:2007-01 Issue:1 Volume:42 Page:193-200
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Kyu-hyoun,Chung Hoe-Ju,Kim Woo-Seop,Park Moonsook,Jang Young-Chan,Kim Jin-Young,Park Hwan-Wook,Kang Uksong,Coteus Paul W.,Choi Joo Sun,Kim Changhyun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4039574/04039590.pdf?arnumber=4039590

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique;Circuits, Systems, and Signal Processing;2022-10-17

2. Memories;Nanometer CMOS ICs;2017

3. BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel;IEEE Journal of Solid-State Circuits;2009-11

4. An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion;IEEE Journal of Solid-State Circuits;2008-01

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