1. A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM
2. A fast 8K × 8 mixed CMOS static RAM
3. A 21-mW 4-Mb CMOS SRAM for battery operation
4. , , , , , , , . A 4.8-ns random access 144-Mb twin-cell memory fabricated using 0.11-µm cost-effective DRAM technology. VLSI Tech Digest, p 188–189, 2004.
5. , , , , , , , , , , . Soft error free, low power and low cost superSRAM with 0.98µm2 cell by utilizing existing 0.15µm-DRAM process, VLSI Tech Digest, p 232–233, 2004.