Vision chip architecture using general-purpose processing elements for 1 ms vision system-Reference-Cited by-同舟云学术

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Vision chip architecture using general-purpose processing elements for 1 ms vision system

Published: Issue: Volume: Page:
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Container-title:Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97
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Author:

Komuro T.,Ishii I.,Ishikawa M.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx4/4997/13717/00632052.pdf?arnumber=632052

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. System-level design space identification for Many-Core Vision Processors;Microprocessors and Microsystems;2017-07

2. High-speed visual feedback for realizing high-performance robotic manipulation;SPIE Proceedings;2017-02-20

3. Parallel Computation of the Region-Based Level Set Method for Boundary Detection of Moving Objects;Journal of Robotics and Mechatronics;2009-12-20

4. Parallel Region-Based Level Set Method with Displacement Correction for Tracking a Single Moving Object;Advanced Concepts for Intelligent Vision Systems;2009

5. A Self-Reconfigurable Implementation of the JPEG Encoder;2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP);2007-07

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