Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models-Reference-Cited by-同舟云学术

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Published:2021-12 Issue:2 Volume:7 Page:193-200
ISSN:2329-9231
Container-title:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
language:
Short-container-title:IEEE J. Explor. Solid-State Comput. Devices Circuits

Author:

Saligram Rakshith^ORCID,Chakraborty Wriddhi^ORCID,Cao Ningyuan,Cao Yu^ORCID,Datta Suman^ORCID,Raychowdhury Arijit^ORCID

Funder

Samsung Global Research Outreach (GRO) Program

National Security Agency (NSA) Laboratory for Physical Sciences

Semiconductor Research Corporation (SRC) through Applications and Systems-Driven Center for Energy-Efficient Integrated NanoTechnologies (ASCENT) Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/6570653/9650774/09627705.pdf?arnumber=9627705

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1. Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05

2. Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures;Japanese Journal of Applied Physics;2024-03-22

3. The Future is Frozen: Cryogenic CMOS for High-Performance Computing (Invited);Chip;2023-12

4. Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures;IEEE Electron Device Letters;2023-09

5. Cryogenic CMOS as an Enabler for Low Power Dynamic Logic;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07