Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8712125/8720395/08720580.pdf?arnumber=8720580
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
2. Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
3. Impact of a Deep Junction Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate NMOS Clamp;2023 45th Annual EOS/ESD Symposium (EOS/ESD);2023-10-02
4. Current Scalability Issues in Multi-Bank 5V PMOS ESD structures: Root cause and Design Guideline;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
5. Unique Rise Time Sensitivity Leading to Air Discharge System-Level ESD Failures in Bidirectional High Voltage SCRs;IEEE Transactions on Electron Devices;2022-05
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