Impact of a Deep Junction Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate NMOS Clamp
Author:
Affiliation:
1. Texas Instruments,Analog Technology Development,Dallas,TX,USA,75243
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10287717/10287664/10287738.pdf?arnumber=10287738
Reference11 articles.
1. P-type isolated GGNMOS with a deep current path for ESD protection
2. Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS
3. Influence of gate length on ESD-performance for deep sub micron CMOS technology;bock;Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396),1999
4. Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 ?m CMOS process;amerasekera;IEDM Tech Dig,1996
5. Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes
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