Current Scalability Issues in Multi-Bank 5V PMOS ESD structures: Root cause and Design Guideline
Author:
Affiliation:
1. Analog Technology Development, Texas Instruments Inc.,Bangalore,Karnataka,India
2. Analog Technology Development, Texas Instruments Inc.,Dallas,Texas,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10117950.pdf?arnumber=10117950
Reference6 articles.
1. The relevance of long-duration TLP stress on system level ESD design;boselli;Electrical Overstress/Electrostatic Discharge Symposium Proceedings,2010
2. A Low Leakage Low Cost-PMOS Based Power Supply Clamp with Active Feedback for ESD Protection in 65nm CMOS Technologies;jeremy c smith;2005 Electrical Overstress/Electrostatic Discharge Symposium eos/esd,2005
3. Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages
4. Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability
5. ESD in Silicon Integrated Circuits
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