Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances-Reference-Cited by-同舟云学术

Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Published:2008-05 Issue:5 Volume:55 Page:1259-1264
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Noori Atif M.,Balseanu Mihaela,Boelen Pieter,Cockburn Andrew,Demuynck Steven,Felch Susan,Gandikota Srinivas,Gelatos A. Jerry,Khandelwal Amit,Kittl Jorge A.,Lauwers Anne,Lee Wen-Chin,Lei Jianxin,Mandrekar Tushar,Schreutelkamp Robert,Shah Kavita,Thompson Scott E.,Verheyen Peter,Wang Ching-Ya,Xia Li-Qun,Arghavani Reza

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/4494714/04475510.pdf?arnumber=4475510

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