1. Chan V, Rengarajan R, Rovedo N, Jin W, Hook T, Nguyen P et al (2003) High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering. In: IEEE international electron devices meeting, 2003. IEDM’03 Technical Digest, pp 3.8. 1–3.8. 4
2. Bai P, Auth C, Balakrishnan S, Bost M, Brain R, Chikarmane V et al (2004) A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm 2 SRAM cell. In: IEEE international electron devices meeting, 2004. IEDM Technical Digest, pp 657–660
3. Chidambaram P, Smith B, Hall L, Bu H, Chakravarthi S, Kim Y et al (2004) 35 drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS. In: 2004 symposium on VLSI technology, 2004. Digest of technical papers, pp 48–49
4. Thompson SE, Armstrong M, Auth C, Cea S, Chau R, Glass G et al (2004) A logic nanotechnology featuring strained-silicon. IEEE Electron Dev Lett 25:191–193
5. Thompson S, Anand N, Armstrong M, Auth C, Arcot B, Alavi M et al. (2002) A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell. In: International electron devices meeting, 2002. IEDM’02, pp 61–64