Author:
Chen Ren,Prasanna Viktor K.
Cited by
6 articles.
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1. TIE;Proceedings of the 46th International Symposium on Computer Architecture;2019-06-22
2. Optimal Circuits for Parallel Bit Reversal;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
3. Arbitrary streaming permutations with minimum memory and latency;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07
4. Optimal dynamic data layouts for 2D FFT on 3D memory integrated FPGA;The Journal of Supercomputing;2016-06-10
5. Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA;Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2015-02-22