Optimal Circuits for Parallel Bit Reversal-Reference-Cited by-同舟云学术

Optimal Circuits for Parallel Bit Reversal

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
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Author:

Chen Ren¹,Prasanna Viktor K.¹

Affiliation:

1. Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3062295

Reference23 articles.

1. Hardware Generator for designs in this paper. http://www-scf.usc.edu/~renchen/. Hardware Generator for designs in this paper. http://www-scf.usc.edu/~renchen/.

2. SPIRAL Hardware Generator. http://www.spiral.net/hardware.html. SPIRAL Hardware Generator. http://www.spiral.net/hardware.html.

3. XST user guide for Virtex-6 Spartan-6 and 7 series devices. http://www.xilinx.com/support/documentation. XST user guide for Virtex-6 Spartan-6 and 7 series devices. http://www.xilinx.com/support/documentation.

4. Pipelined Parallel FFT Architectures via Folding Transformation

5. Optimal Rearrangeable Multistage Connecting Networks

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