Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA

Author:

Chen Ren1,Siriyal Sruja1,Prasanna Viktor1

Affiliation:

1. University of Southern California, Los Angeles, CA, USA

Funder

National Science Foundation

Defense Advanced Research Projects Agency

Publisher

ACM

Reference28 articles.

1. DDR4 SDRAM. http://www.micron.com/products/dram/ddr4-sdram. DDR4 SDRAM. http://www.micron.com/products/dram/ddr4-sdram.

2. Vivado design suite user guide: design flows overview. http://www.xilinx.com/support/documentation/. Vivado design suite user guide: design flows overview. http://www.xilinx.com/support/documentation/.

3. XST user guide for Virtex-6 Spartan-6 and 7 series devices. http://www.xilinx.com/support/documentation. XST user guide for Virtex-6 Spartan-6 and 7 series devices. http://www.xilinx.com/support/documentation.

4. An 0(n log n) sorting network

5. FlexGrip: A soft GPGPU for FPGAs

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