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All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

  • Published:2017-05 Issue:5 Volume:64 Page:2080-2085
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Karatsori Theano A.ORCID,Theodorou Christoforos G.,Josse Emmanuel,Dimitriadis Charalabos A.ORCID,Ghibaudo G.

Funder

ECSEL WaytoGo Fast European project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

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1. Characteristics Fluctuation of Sub-3-nm Bulk FinFET Devices Induced by Random Interface Traps;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02

2. Reconfigurable Leakage-based Weak PUF in 65nm CMOS with 0.63% instability;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. Analysis and Modeling of Current Mismatch in Negative Capacitance Field-Effect Transistor;IEEE Transactions on Electron Devices;2022-09

4. Variability Modeling in Triple-Gate Junctionless Nanowire Transistors;IEEE Transactions on Electron Devices;2022-08

5. Accounting for Current Degradation Effects in the Compact Noise Modeling of Nano-scale MOSFETs;2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST);2022-06-08
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