A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure-Reference-Cited by-同舟云学术

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A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure

Published:2023 Issue: Volume:11 Page:89298-89308
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Li Zheng¹^ORCID,Yang Yating¹^ORCID,Liu Mingyang²,Liu Wei²,Hou Ying¹^ORCID,Wei Zihui¹,Wang Xiaosong¹,Li Zhenming²,Huang Shuilong¹,Liu Yu¹^ORCID

Affiliation:

1. Research and Development Center of Healthcare Electronics, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China

2. Energy Storage and Electrotechnics Department, China Electric Power Research Institute Company Ltd., Beijing, China

Funder

Science and Technology Program from State Grid Corporation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10217817.pdf?arnumber=10217817

Reference23 articles.

1. An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS

2. A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

3. Non-binary digital calibration for split-capacitor DAC in SAR ADC

4. Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

5. A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs;wu;Proc IEEE Int Symp Circuits Syst (ISCAS),2013

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15

2. Reducing the power consumption of level-crossing analog-to-digital converters by using a signal activity monitoring circuit;Microelectronics Journal;2023-12

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