A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR-Reference-Cited by-同舟云学术

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A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

Published:2019-04 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Kim Taewoong,Chae Youngcheol

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8767369/8780115/08780230.pdf?arnumber=8780230

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Power-Efficient Autonomous Current Adaptation ADC Input Driver;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic;Journal of Semiconductors;2024-06-01

3. A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations;Chips;2024-05-10

4. A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC;Microelectronics Journal;2024-02

5. A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction;IEEE Journal of Solid-State Circuits;2023-02

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