A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers
Author:
Affiliation:
1. DIEEI, Università degli Studi di Catania, Catania, Italy
2. DIIET, Università degli Studi di Roma ‘‘La Sapienza,’’, Rome, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09893810.pdf?arnumber=9893810
Reference27 articles.
1. Characterization and Application of a Pseudorandom Impulse Sequence for Parameter Estimation Applications
2. Criteria to Improve Time-Delay Estimation of Spread Spectrum Signals in Satellite Positioning
3. Blind Estimation of Self-Synchronous Scrambler Using Orthogonal Complement Space in DSSS Systems
4. High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
5. A Low-Power Parallel Architecture for Linear Feedback Shift Registers
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