Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors
Author:
Affiliation:
1. Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09968000.pdf?arnumber=9968000
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