Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy-Reference-Cited by-同舟云学术

Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy

Published:2023-11-29 Issue: Volume: Page:363-368
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
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Author:

Barbirotta Marcello^ORCID,Menichelli Francesco^ORCID,Mastrandrea Antonio^ORCID,Cheikh Abdallah^ORCID,Jamili Saeid^ORCID,Angioli Marco^ORCID,Olivieri Mauro^ORCID

Publisher

Springer Nature Switzerland

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-48711-8_44

Reference17 articles.

1. Barbirotta, M., et al.: Fault-tolerant hardware acceleration for high-performance edge-computing nodes. Electronics 12(17) (2023). https://doi.org/10.3390/electronics12173574, https://www.mdpi.com/2079-9292/12/17/3574

2. Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F., Olivieri, M.: Analysis of a fault tolerant edge-computing microarchitecture exploiting vector acceleration. In: 2022 17th Conference on Ph. D Research in Microelectronics and Electronics (PRIME), pp. 237–240. IEEE (2022)

3. Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F., Olivieri, M.: Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors. IEEE Access 10, 126074–126088 (2022)

4. Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F., Ottavi, M., Olivieri, M.: Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core. J. Low Power Electron. Appli. 13(1) (2023). https://doi.org/10.3390/jlpea13010002, https://www.mdpi.com/2079-9268/13/1/2

5. Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F., Vigli, F., Olivieri, M.: A fault tolerant soft-core obtained from an interleaved-multi-threading risc-v microprocessor design. In: 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1–4. IEEE (2021)