SHAKTI-F: A Fault Tolerant Microprocessor Architecture
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7421875/7422217/07422253.pdf?arnumber=7422253
Cited by 27 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Exploring Error Correction Circuits on RISC-V based Systems for Space Applications;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. SHAKTI Dual Lockstep Microprocessor: Ensuring Functional Integrity for Robust Computing;2024 IEEE International Conference on Contemporary Computing and Communications (InC4);2024-03-15
3. Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital;Microprocessors and Microsystems;2024-03
4. Early Execution for Soft Error Detection;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
5. Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space;ACM Transactions on Cyber-Physical Systems;2023-11-30
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