A Nanoscale Memory and Transistor Using Backside Trapping
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://xplorestaging.ieee.org/ielx5/7729/28953/01303520.pdf?arnumber=1303520
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage;JSTS:Journal of Semiconductor Technology and Science;2015-04-30
2. Demonstration of Unified Memory in FinFETs;International Journal of High Speed Electronics and Systems;2014-09
3. Remote carrier trapping in FinFETs with ONO buried layer: Temperature effects;Microelectronics Reliability;2013-03
4. Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations;Japanese Journal of Applied Physics;2011-08-22
5. Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations;Japanese Journal of Applied Physics;2011-08-01
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