Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4832838/4897524/04897602.pdf?arnumber=4897602
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Thermal influence on performance characteristics of double gate MOSFET biosensors with gate stack configuration;Discover Applied Sciences;2024-08-17
2. Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs;Micromachines;2022-06-24
3. Suppression of buried oxide induced variability on digital performance of GeOI pMOSFETs using substrate bias scheme;Microsystem Technologies;2019-11-28
4. Enhancing digital performance of nanoscale GeOI MOSFETs through optimization of buried oxide properties and channel thickness;Microsystem Technologies;2018-09-11
5. Studies of buried oxide properties on nanoscale GeOI pMOSFETs for design of a high performance common source amplifier;Materials Science in Semiconductor Processing;2018-06
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