Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology-Reference-Cited by-同舟云学术

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Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology

Published:2023-04-28 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Computational Intelligence and Sustainable Engineering Solutions (CISES)
language:
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Author:

Rakesh ¹,Shah Owais Ahmad²,Vats Satvik³

Affiliation:

1. Jaypee Institute of Information Technology,Department of Electronics & Communication Engineering,Noida,India

2. Noida International University,Department of Electronics & Communication Engineering,Gautam Budh Nagar,India

3. Graphic Era Hill University,Department of Computer Science & Engineering,Dehradun,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10183385/10182405/10183608.pdf?arnumber=10183608

Reference15 articles.

1. High speed and low cost synchronous counter design in quantum-dot cellular automata

2. The Design of the Moebius Mod-6 Counter Using Electronic Workbench Software

3. Design and Implementation of an On-Chip Test Generation Scheme Based on Reconfigurable Run-Time Programmable and Multiple Twisted-Ring Counters

4. Design and performance study of the TOP counter

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET;2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE);2023-11-23

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