Low Inductance PCB Layout for GaN Devices: Interleaving Scheme
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9486978/9486980/09487045.pdf?arnumber=9487045
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. PCB Layout Evaluation of GaN HEMT Power Loop;2023 IEEE 2nd International Power Electronics and Application Symposium (PEAS);2023-11-10
2. Three-Dimensional Lattice Structure to Reduce Parasitic Inductance for WBG Power Semiconductor-Based Converters;Electronics;2023-04-09
3. PCB Design Impact on GaN-Based Converter Operation;2023 IEEE Applied Power Electronics Conference and Exposition (APEC);2023-03-19
4. Multi-Pulse Si-MOSFET Gate Driving Utilizing Gate Loop Inductance;IEEE Open Journal of Power Electronics;2023
5. A Highly Integrated GaN Power Module with Low Parasitic Inductance and High Thermal Performance;2022 IEEE Energy Conversion Congress and Exposition (ECCE);2022-10-09
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