Three-Dimensional Lattice Structure to Reduce Parasitic Inductance for WBG Power Semiconductor-Based Converters

Abstract

Wide bandgap (WBG) power semiconductors can achieve high efficiency and power density due to their low on-resistance and fast switching speeds. However, the fast-switching speed induces voltage to the parasitic inductance in the circuit, causing a significant overshoot in the drain-source voltage of the devices and the ringing of the drain current due to resonance with the parasitic capacitance. Thus, minimizing parasitic inductance is necessary for driving WBG power semiconductors in a stable manner. This paper proposes a three-dimensional lattice structure that reduces parasitic inductance through horizontal and vertical magnetic flux cancellations within a printed circuit board (PCB). The relationship between the magnetic flux cancellation and the parasitic inductance is analyzed, and the magnetic flux cancellation in the proposed structure is described. In addition, a practical PCB layout design procedure based on the proposed structure is provided. Simulation results demonstrate a 55.8% reduction in parasitic inductance, and experimental results show reduced overshoot and ringing at the switching transient, resulting in a 26% reduction in switching loss. As a result, the proposed method can improve the efficiency and stability of WBG device-based power converters.