High speed fixed point dividers for FPGAs-Reference-Cited by-同舟云学术

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High speed fixed point dividers for FPGAs

Published:2009-08 Issue: Volume: Page:
ISSN:
Container-title:2009 International Conference on Field Programmable Logic and Applications
language:
Short-container-title:

Author:

Sutter Gustavo,Deschamps Jean-Pierre

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5247666/5272229/05272492.pdf?arnumber=5272492

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. GSGP-hardware: instantaneous symbolic regression with an FPGA implementation of geometric semantic genetic programming;Genetic Programming and Evolvable Machines;2024-06-25

2. Area efficient high-speed binary divider using Xilinx IP core;AIP Conference Proceedings;2024

3. Design and Implementation of 32-bit Signed Divider for VLSI Applications;2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2023-11-22

4. Geometric Transformations;Design for Embedded Image Processing on FPGAs;2023-09-05

5. Coarse-Grained High-speed Reconfigurable Array-based Approximate Accelerator for Deep Learning Applications;2023 57th Annual Conference on Information Sciences and Systems (CISS);2023-03-22

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