Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5223291/5223292/05223359.pdf?arnumber=5223359
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units;IEEE Transactions on Computers;2023-10
2. Low Latency Floating-Point Division and Square Root Unit;IEEE Transactions on Computers;2020-02-01
3. Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-04
4. A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques;Proceedings of the 2016 International Symposium on Low Power Electronics and Design;2016-08-08
5. A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture;Arabian Journal for Science and Engineering;2016-03-30
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