Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add
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Published:2018-04
Issue:4
Volume:26
Page:639-652
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ISSN:1063-8210
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Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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language:
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Short-container-title:IEEE Trans. VLSI Syst.
Author:
Ratkovic IvanORCID,
Palomar Oscar,
Stanic Milan,
Unsal Osman Sabri,
Cristal Adrian,
Valero Mateo
Funder
RoMoL ERC Advanced Grant
European Union (FEDER funds)
FPU research grant from the Spanish MECD
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
1 articles.
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