A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques
Author:
Affiliation:
1. Barcelona Supercomputing Center and Polytechnic University of Catalonia
2. Barcelona Supercomputing Center
3. Barcelona Supercomputing Center and Polytechnic University of Catalonia and Centro Superior de Investigaciones Cientificas (IIIA-CSIC)
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2934583.2934587
Reference22 articles.
1. Berkeley hardware floating-point units. https://github.com/ucb-bar/berkeley-hardfloat/ 2015. Berkeley hardware floating-point units. https://github.com/ucb-bar/berkeley-hardfloat/ 2015.
2. Reference Manual for ARM Architecture - ARMv7-A. http://arm.com/ 2015. Reference Manual for ARM Architecture - ARMv7-A. http://arm.com/ 2015.
3. Chisel
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
2. Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-04
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