Thermal-Aware Optimization of SoC Floorplan with Heterogenous Multi-Cores
Author:
Affiliation:
1. System LSI Samsung Electronics Co., Ltd,Hwaseong-si,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9899435/9899496/09899498.pdf?arnumber=9899498
Reference7 articles.
1. System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs;nandakumar;2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC),0
2. Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs
3. Impact of Chip, Package, and Set Design on Transient Temperature in Mobile Application
4. Simulated annealing based thermal-aware floorplanning
5. Methodology for 3D Package Selection using Thermal Violation Region Graph
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1. Enhance Power and Temperature Control During Thermal Interference Events in Hybrid Core SoC Architecture;2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT);2023-07-14
2. Design space exploration (DSE) for over-136GB/s IO bandwidth with LPDDR5X SDRAM packages on SOC package in 200mm3;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
3. Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs);2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
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