Enhance Power and Temperature Control During Thermal Interference Events in Hybrid Core SoC Architecture
Author:
Affiliation:
1. Design Engineering Group Intel Corporation,Bengaluru,India
2. Design Engineering Group Intel Corporation,Oregon,United States
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10234680/10234728/10234732.pdf?arnumber=10234732
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5. Secure, Scalable and Low-Power Junction Temperature Sensing for Multi-Processor Systems-on-Chip 2020 21st;kumar;International Symposium on Quality Electronic Design (ISQED),2020
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