Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices-Reference-Cited by-同舟云学术

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Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices

Published:2007-09 Issue:5 Volume:22 Page:1847-1856
ISSN:0885-8993
Container-title:IEEE Transactions on Power Electronics
language:
Short-container-title:IEEE Trans. Power Electron.

Author:

Biondi Tonio,Greco Giuseppe,Allia Maria Concetta,Liotta Salvatore Fabio,Bazzano Gaetano,Rinaudo Salvatore

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/63/4300856/04300858.pdf?arnumber=4300858

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Role of the Gate Resistance and Device Variability on the Dynamic Performance of Parallel SiC Power MOSFETs;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02

2. Physical insight into turn‐on transient of silicon carbide gate turn‐off thyristor;IET Power Electronics;2024-05

3. Distributed field plate effects in split-gate trench MOSFETs;2023 35th International Conference on Microelectronic Test Structure (ICMTS);2023-03-27

4. Thermal Mitigation and Optimization Via Multitier Bond Wire Layout for IGBT Modules Considering Multicellular Electro-Thermal Effect;IEEE Transactions on Power Electronics;2022-06

5. Modeling of In-chip Current-Temperature Distribution of SiC Power MOSFETs during Fast Switching Events;2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2022-05-22

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