Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency-Reference-Cited by-同舟云学术

Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

Published:2022-04 Issue:4 Volume:58 Page:1-11
ISSN:0018-9464
Container-title:IEEE Transactions on Magnetics
language:
Short-container-title:IEEE Trans. Magn.

Author:

Yamani Sudha Vani¹,Rani N. Usha¹,Vaddi Ramesh²^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, Vignan’s Foundation for Science, Technology and Research University, Guntur, Andhra Pradesh, India

2. Department of Electronics and Communication Engineering, School of Engineering and Applied Sciences, SRM University, Amaravati, Andhra Pradesh, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/20/9737705/09686706.pdf?arnumber=9686706

Reference45 articles.

1. Stack based sense amplifier designs for reducing input-referred offset

2. Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

3. Tunnel FET RF Rectifier Design for Energy Harvesting Applications

4. Analog Circuit Design Using Tunnel-FETs

5. Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

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