Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET-Reference-Cited by-同舟云学术

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Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET

Published:2019-07 Issue:7 Volume:66 Page:2898-2903
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kim Hyunsuk^ORCID,Son Dokyun^ORCID,Myeong Ilho^ORCID,Ryu Donghyun^ORCID,Park Jaeyeol,Kang Myounggon^ORCID,Jeon Jongwook^ORCID,Shin Hyungcheol

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/8736764/08728184.pdf?arnumber=8728184

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective;Journal of Applied Physics;2024-03-12

2. Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs;IEEE Transactions on Nanotechnology;2024

3. Improvement of Thermal Characteristics and On-Current in Vertically Stacked Nanosheet FET by Parasitic Channel Height Engineering;IEEE Access;2024

4. Investigation and optimization of electro-thermal performance of Double Gate-All-Around MOSFET;Microelectronics Journal;2022-11

5. Impact of Process Fluctuations on RF Small-Signal Parameter of Gate-All-Around Nanosheet Transistor Beyond 3 nm Node;IEEE Transactions on Electron Devices;2022-01

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