A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology-Reference-Cited by-同舟云学术

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A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology

Published:2022-10-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
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Author:

Madhvaraj Manasa¹,Mir Salvador¹,Barragan Manuel J.¹

Affiliation:

1. Univ. Grenoble Alpes,CNRS, TIMA,Grenoble,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9939277/9939284/09939620.pdf?arnumber=9939620

Reference14 articles.

1. An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience

2. A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

3. A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

4. Design of sub-10-picoseconds on-chip time measurement circuit

5. On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

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