On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Author:

Liang Joshua,Jalali Mohammad Sadegh,Sheikholeslami Ali,Kibune Masaya,Tamura Hirotaka

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Jitter-Based Authentication for Automotive Wireline Networks;IEEE Access;2024

2. A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2023-11

3. A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

4. A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-10

5. A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method;2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID);2022-02

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