A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI-Reference-Cited by-同舟云学术

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A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

Published:2016-09 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
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Author:

Sourikopoulos Ilias,Frappe Antoine,Cathelin Andreia,Clavier Laurent,Kaiser Andreas

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7585490/7598228/07598263.pdf?arnumber=7598263

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology;Microelectronics Journal;2024-09

2. A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

3. A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

4. Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation;2023 IEEE 24th Latin American Test Symposium (LATS);2023-03-21

5. Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies;2023 IEEE 24th Latin American Test Symposium (LATS);2023-03-21

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