Using Custom Fault Models to Improve Understanding of Silicon Failures

Author:

Kundu Subhadip1,Bhargava Gaurav2,Endrinal Lesly3,Ranganathan Lavakumar3

Affiliation:

1. QCT Mobile SIM Bangalore, Qualcomm India Pvt. Ltd.

2. QCT Product and Test Engineering, Qualcomm Technologies Inc.

3. Ranganathan QCT Failure Analysis, Qualcomm Technologies Inc.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Customizing ATPG User-Defined Stresses and Tests To Target Cell-Neighborhood-Bridging Defects;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

2. Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14

4. Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis;2023 IEEE International Test Conference (ITC);2023-10-07

5. Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes;2023 IEEE International Test Conference (ITC);2023-10-07

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