Improving CMOS open defect coverage using hazard activated tests
Author:
Han Chao,Singh Adit D.
Cited by
3 articles.
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1. New Approaches of Side-Channel Attacks Based on Chip Testing Methods;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05
2. Using Custom Fault Models to Improve Understanding of Silicon Failures;2022 IEEE International Test Conference (ITC);2022-09
3. Harzard-Based ATPG for Improving Delay Test Quality;Journal of Electronic Testing;2015-01-11