A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA

Author:

Fong Chi Fung Brian,Mu Jiandong,Zhang Wei

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Jumping Shift: A Logarithmic Quantization Method for Low-Power CNN Acceleration;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

2. Area Efficient Compression for Floating-Point Feature Maps in Convolutional Neural Network Accelerators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02

3. High-Performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System;ACM Transactions on Embedded Computing Systems;2022-05-02

4. Processor Architecture Optimization for Spatially Dynamic Neural Networks;2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC);2021-10-04

5. Efficient field‐programmable gate array‐based reconfigurable accelerator for deep convolution neural network;Electronics Letters;2021-02-23

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