Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning
Author:
Affiliation:
1. National Yang Ming Chiao Tung University,Department of Electronics and Electrical Engineering & Institute of Electronics,Hsinchu,Taiwan
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168572.pdf?arnumber=10168572
Reference18 articles.
1. A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing
2. A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing
3. Design of Power Efficient Posit Multiplier
4. New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference
5. A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing
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