Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning
Author:
Affiliation:
1. University of Illinois at Chicago (UIC),AEON Lab,Chicago,IL,USA
2. Fermi National Accelerator Lab (FNAL),Batavia,IL,USA
3. Intel Corp.,Hillsboro,OR,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168632.pdf?arnumber=10168632
Reference19 articles.
1. MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference
2. A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
3. A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array
4. Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors
5. A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC
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