Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9420829/9420830/09420942.pdf?arnumber=9420942
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Machine Learning-Assisted Multiobjective Optimization of Advanced Node Gate-All-Around Transistor for Logic and RF Applications;IEEE Transactions on Electron Devices;2024-02
2. Improvement of Thermal Characteristics and On-Current in Vertically Stacked Nanosheet FET by Parasitic Channel Height Engineering;IEEE Access;2024
3. Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors;Journal of Electrical Engineering;2023-12-01
4. Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs;Solid-State Electronics;2023-11
5. Discussion on the Main Mechanisms Contributing to the 1/f Noise in GAA Si VNW pMOSFETs;2023 International Conference on Noise and Fluctuations (ICNF);2023-10-17
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