Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs-Reference-Cited by-同舟云学术

Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs

Published:2023-11 Issue: Volume:209 Page:108709
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Tahiat A.^ORCID,Cretu B.^ORCID,Veloso A.,Simoen E.^ORCID

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. Low-Frequency Noise Assessment of Vertically Stacked Si n-Channel Nanosheet FETs With Different Metal Gates;Oliveira;IEEE Trans Electron Devices,2020

2. Veloso A, et al. “Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling,” 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Chengdu, China, 2021, pp. 1-3. https://doi.org/10.1109/EDTM50988.2021.9420942.

3. Simoen E, et al. “Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?” 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Caen, France, 2020, pp. 1-6. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365338.

4. Diameter Scaling of Vertical Ge Gate-All-Around Nanowire pMOSFETs;Liu;IEEE Trans Electron Devices,2020

5. Simoen E, Veloso A, Matagne P. “On the Asymmetry of the DC and Low-Frequency Noise Characteristics of Vertical Nanowire pMOSFETs with Bulk Source Contact,” 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Caen, France, 2021, pp. 1-4. https://doi.org/10.1109/EuroSOI-ULIS53016.2021.9560186.

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1. Is there a limit when the access resistance impact on the extraction of key GAA NS FETs devices parameters can (not) be avoided?;Solid-State Electronics;2023-11

2. Discussion on the Main Mechanisms Contributing to the 1/f Noise in GAA Si VNW pMOSFETs;2023 International Conference on Noise and Fluctuations (ICNF);2023-10-17