A 4.5 ns access time 1K x 4 bit ECL RAM-Reference-Cited by-同舟云学术

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A 4.5 ns access time 1K x 4 bit ECL RAM

Published:1983-10 Issue:5 Volume:18 Page:515-520
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nokubo J.,Tamura T.,Nakamae M.,Shiraki H.,Ikushima T.,Akashi T.,Mayumi H.,Kubota T.,Nakamura T.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22591/01051986.pdf?arnumber=1051986

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characteristics of high-speed bipolar RAMs under address-skew condition;Electronics and Communications in Japan (Part II: Electronics);1992

2. MOS and Bipolar Memory Circuit Techniques;IETE Journal of Research;1990-05

3. Effect of conventional and rapid thermal annealing on platinum silicide Schottky barrier diodes;Applied Physics Letters;1990-01-08

4. Design for reducing alpha-particle-induced soft errors in ECL logic circuitry;IEEE Journal of Solid-State Circuits;1989-10

5. A bipolar ECL static RAM using polysilicon-diode loaded memory cell;IEEE Journal of Solid-State Circuits;1989-04

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