Sample-set differential logic (SSDL) for complex high-speed VLSI-Reference-Cited by-同舟云学术

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Sample-set differential logic (SSDL) for complex high-speed VLSI

Published:1986-04 Issue:2 Volume:21 Page:367-369
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Grotjohn T.A.,Hoefflinger B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22607/01052530.pdf?arnumber=1052530

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes;IEICE Transactions on Electronics;2012

2. High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition;IEICE Transactions on Electronics;2005-10-01

3. Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic;Proceedings of the 17th symposium on Integrated circuits and system design - SBCCI '04;2004

4. Race logic architecture (RALA): a novel logic concept using the race scheme of input variables;IEEE Journal of Solid-State Circuits;2002

5. A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches;Lecture Notes in Computer Science;2002

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