CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes
Author:
Affiliation:
1. Graduate Institute Of Electrical Engineering, National Taipei University
2. Department of Electronic Engineering Fu-Jen Catholic University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E95.C/2/E95.C_2_275/_pdf
Reference32 articles.
1. [1] Y. Suzuki. K, Odagawa, and T. Abe, “Clocked CMOS calculator circuitry,” IEEE J. Solid-State Circuits, vol.SC-8, pp.462-469, Dec. 1973.
2. [2] N. Weste and K. Eshraghian, Principles of CMOS VLSI design, Addison-Wesley, 1985.
3. [3] T.A. Grotjohn and B. Hoefflinger, “Sample-set differential logic (SSDL) for complex high speed VLSI,” IEEE J. Solid-State Circuits, vol.21, pp.367-369, April 1986.
4. [4] S.L. Lu, “Implementation of iterative networks with CMOS differential logic,” IEEE J. Solid-State Circuits, vol.23, pp.1013-1017, Aug. 1988.
5. [5] S.L. Lu and L.M.D. Ercegovac, “Evaluation of two-summand adders implemented in ECDL CMOS differential logic,” IEEE J. Solid-State Circuits, vol.26, pp.1152-1160, Aug. 1991.
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