Source Extended GaSb/GaAs Heterojunction GAATFET to Improve ION/IOFF Ratio
Author:
Affiliation:
1. VIT-AP University,School of Electronics Engineering,Amaravati,India
2. Adama Science and Technology University,Department of ECE,Adama,Ethiopia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10032824/10032825/10032826.pdf?arnumber=10032826
Reference27 articles.
1. Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction
2. A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET
3. GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths
4. Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction
5. Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets
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1. GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2023-08-25
2. Demonstration of L-Channel Tunnel FET with Triple Metal Gate for Next Generation IC Technology;2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP);2023-03-18
3. Extended Source Tunnel Field-Effect Transistor with Source Pocket Integration;2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP);2023-03-18
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